Syntax of GFX10 RDNA2 Instructions — LLVM 18.1.8 documentation

# Syntax of GFX10 RDNA2 Instructions

## Introduction

This document describes the syntax of GFX10 RDNA2 instructions.

GFX10 RDNA2 family includes gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035 and gfx1036 GPUs.

## Notation

Notation used in this document is explained here.

## Overview

An overview of generic syntax and other features of AMDGPU instructions may be found in this document.

## Instructions

### DPP16

    INSTRUCTION              DST0       DST1 SRC0         SRC1        SRC2  MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add_co_ci_u32_dpp      vdst,      vcc, vsrc0,       vsrc1,      vcc   dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_add_f16_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_add_f32_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_add_nc_u32_dpp         vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_and_b32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ashrrev_i32_dpp        vdst,           vsrc0:u32,   vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_bfrev_b32_dpp          vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ceil_f16_dpp           vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ceil_f32_dpp           vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cndmask_b32_dpp        vdst,           vsrc0:m,     vsrc1:m,    vcc   dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cos_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cos_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f16_f32_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f16_i16_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f16_u16_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_f16_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_i32_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_u32_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_ubyte0_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_ubyte1_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_ubyte2_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_f32_ubyte3_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_flr_i32_f32_dpp    vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_i16_f16_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_i32_f32_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_norm_i16_f16_dpp   vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_norm_u16_f16_dpp   vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_off_f32_i4_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_pkrtz_f16_f32_dpp  vdst,           vsrc0:m:f32, vsrc1:m:f32       dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_rpi_i32_f32_dpp    vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_u16_f16_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_cvt_u32_f32_dpp        vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_dot2c_f32_f16_dpp      vdst,           vsrc0:f16x2, vsrc1:f16x2       dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_dot4c_i32_i8_dpp       vdst,           vsrc0:i8x4,  vsrc1:i8x4        dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_exp_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_exp_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ffbh_i32_dpp           vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ffbh_u32_dpp           vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ffbl_b32_dpp           vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_floor_f16_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_floor_f32_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_fmac_f16_dpp           vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_fmac_f32_dpp           vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_fract_f16_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_fract_f32_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_frexp_exp_i16_f16_dpp  vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_frexp_exp_i32_f32_dpp  vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_frexp_mant_f16_dpp     vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_frexp_mant_f32_dpp     vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_ldexp_f16_dpp          vdst,           vsrc0:m,     vsrc1:i16         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_log_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_log_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_lshlrev_b32_dpp        vdst,           vsrc0:u32,   vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_lshrrev_b32_dpp        vdst,           vsrc0:u32,   vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_max_f16_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_max_f32_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_max_i32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_max_u32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_min_f16_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_min_f32_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_min_i32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_min_u32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mov_b32_dpp            vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_movreld_b32_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_movrels_b32_dpp        vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_movrelsd_2_b32_dpp     vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_movrelsd_b32_dpp       vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_f16_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_f32_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_hi_i32_i24_dpp     vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_hi_u32_u24_dpp     vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_i32_i24_dpp        vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_legacy_f32_dpp     vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_mul_u32_u24_dpp        vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_not_b32_dpp            vdst,           vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_or_b32_dpp             vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rcp_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rcp_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rcp_iflag_f32_dpp      vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rndne_f16_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rndne_f32_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rsq_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_rsq_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sat_pk_u8_i16_dpp      vdst:u8x4,      vsrc                           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sin_f16_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sin_f32_dpp            vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sqrt_f16_dpp           vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sqrt_f32_dpp           vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sub_co_ci_u32_dpp      vdst,      vcc, vsrc0,       vsrc1,      vcc   dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sub_f16_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sub_f32_dpp            vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_sub_nc_u32_dpp         vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_subrev_co_ci_u32_dpp   vdst,      vcc, vsrc0,       vsrc1,      vcc   dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_subrev_f16_dpp         vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_subrev_f32_dpp         vdst,           vsrc0:m,     vsrc1:m           dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_subrev_nc_u32_dpp      vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_trunc_f16_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_trunc_f32_dpp          vdst,           vsrc:m                         dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_xnor_b32_dpp           vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi
    v_xor_b32_dpp            vdst,           vsrc0,       vsrc1             dpp16_ctrl row_mask bank_mask bound_ctrl fi

### DPP8

    INSTRUCTION                    DST0       DST1      SRC0         SRC1        SRC2        MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add_co_ci_u32_dpp            vdst,      vcc,      vsrc0,       vsrc1,      vcc         dpp8_sel fi
    v_add_f16_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_add_f32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_add_nc_u32_dpp               vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_and_b32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_ashrrev_i32_dpp              vdst,                vsrc0:u32,   vsrc1                   dpp8_sel fi
    v_bfrev_b32_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_ceil_f16_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_ceil_f32_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_cndmask_b32_dpp              vdst,                vsrc0,       vsrc1,      vcc         dpp8_sel fi
    v_cos_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_cos_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f16_f32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f16_i16_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f16_u16_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_f16_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_i32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_u32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_ubyte0_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_ubyte1_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_ubyte2_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_cvt_f32_ubyte3_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_cvt_flr_i32_f32_dpp          vdst,                vsrc                                 dpp8_sel fi
    v_cvt_i16_f16_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_i32_f32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_norm_i16_f16_dpp         vdst,                vsrc                                 dpp8_sel fi
    v_cvt_norm_u16_f16_dpp         vdst,                vsrc                                 dpp8_sel fi
    v_cvt_off_f32_i4_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_cvt_pkrtz_f16_f32_dpp        vdst,                vsrc0:f32,   vsrc1:f32               dpp8_sel fi
    v_cvt_rpi_i32_f32_dpp          vdst,                vsrc                                 dpp8_sel fi
    v_cvt_u16_f16_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_cvt_u32_f32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_dot2c_f32_f16_dpp            vdst,                vsrc0:f16x2, vsrc1:f16x2             dpp8_sel fi
    v_dot4c_i32_i8_dpp             vdst,                vsrc0:i8x4,  vsrc1:i8x4              dpp8_sel fi
    v_exp_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_exp_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_ffbh_i32_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_ffbh_u32_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_ffbl_b32_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_floor_f16_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_floor_f32_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_fmac_f16_dpp                 vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_fmac_f32_dpp                 vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_fract_f16_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_fract_f32_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_frexp_exp_i16_f16_dpp        vdst,                vsrc                                 dpp8_sel fi
    v_frexp_exp_i32_f32_dpp        vdst,                vsrc                                 dpp8_sel fi
    v_frexp_mant_f16_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_frexp_mant_f32_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_ldexp_f16_dpp                vdst,                vsrc0,       vsrc1:i16               dpp8_sel fi
    v_log_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_log_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_lshlrev_b32_dpp              vdst,                vsrc0:u32,   vsrc1                   dpp8_sel fi
    v_lshrrev_b32_dpp              vdst,                vsrc0:u32,   vsrc1                   dpp8_sel fi
    v_max_f16_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_max_f32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_max_i32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_max_u32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_min_f16_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_min_f32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_min_i32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_min_u32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mov_b32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_movreld_b32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_movrels_b32_dpp              vdst,                vsrc                                 dpp8_sel fi
    v_movrelsd_2_b32_dpp           vdst,                vsrc                                 dpp8_sel fi
    v_movrelsd_b32_dpp             vdst,                vsrc                                 dpp8_sel fi
    v_mul_f16_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_f32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_hi_i32_i24_dpp           vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_hi_u32_u24_dpp           vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_i32_i24_dpp              vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_legacy_f32_dpp           vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_mul_u32_u24_dpp              vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_not_b32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_or_b32_dpp                   vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_rcp_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_rcp_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_rcp_iflag_f32_dpp            vdst,                vsrc                                 dpp8_sel fi
    v_rndne_f16_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_rndne_f32_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_rsq_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_rsq_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_sat_pk_u8_i16_dpp            vdst:u8x4,           vsrc                                 dpp8_sel fi
    v_sin_f16_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_sin_f32_dpp                  vdst,                vsrc                                 dpp8_sel fi
    v_sqrt_f16_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_sqrt_f32_dpp                 vdst,                vsrc                                 dpp8_sel fi
    v_sub_co_ci_u32_dpp            vdst,      vcc,      vsrc0,       vsrc1,      vcc         dpp8_sel fi
    v_sub_f16_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_sub_f32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_sub_nc_u32_dpp               vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_subrev_co_ci_u32_dpp         vdst,      vcc,      vsrc0,       vsrc1,      vcc         dpp8_sel fi
    v_subrev_f16_dpp               vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_subrev_f32_dpp               vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_subrev_nc_u32_dpp            vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_trunc_f16_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_trunc_f32_dpp                vdst,                vsrc                                 dpp8_sel fi
    v_xnor_b32_dpp                 vdst,                vsrc0,       vsrc1                   dpp8_sel fi
    v_xor_b32_dpp                  vdst,                vsrc0,       vsrc1                   dpp8_sel fi

### DS

    INSTRUCTION                    DST         SRC0      SRC1      SRC2           MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————
    ds_add_f32                                 vaddr,    vdata                    offset gds
    ds_add_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_add_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_add_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_add_u32                                 vaddr,    vdata                    offset gds
    ds_add_u64                                 vaddr,    vdata                    offset gds
    ds_and_b32                                 vaddr,    vdata                    offset gds
    ds_and_b64                                 vaddr,    vdata                    offset gds
    ds_and_rtn_b32                 vdst,       vaddr,    vdata                    offset gds
    ds_and_rtn_b64                 vdst,       vaddr,    vdata                    offset gds
    ds_append                      vdst                                           offset gds
    ds_bpermute_b32                vdst,       vaddr,    vdata                    offset
    ds_cmpst_b32                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_b64                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_f32                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_f64                               vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_f32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_cmpst_rtn_f64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_condxchg32_rtn_b64          vdst,       vaddr,    vdata                    offset gds
    ds_consume                     vdst                                           offset gds
    ds_dec_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_dec_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_dec_u32                                 vaddr,    vdata                    offset gds
    ds_dec_u64                                 vaddr,    vdata                    offset gds
    ds_gws_barrier                             vdata                              offset gds
    ds_gws_init                                vdata                              offset gds
    ds_gws_sema_br                             vdata                              offset gds
    ds_gws_sema_p                                                                 offset gds
    ds_gws_sema_release_all                                                       offset gds
    ds_gws_sema_v                                                                 offset gds
    ds_inc_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_inc_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_inc_u32                                 vaddr,    vdata                    offset gds
    ds_inc_u64                                 vaddr,    vdata                    offset gds
    ds_max_f32                                 vaddr,    vdata                    offset gds
    ds_max_f64                                 vaddr,    vdata                    offset gds
    ds_max_i32                                 vaddr,    vdata                    offset gds
    ds_max_i64                                 vaddr,    vdata                    offset gds
    ds_max_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_f64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_i32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_i64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_max_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_max_u32                                 vaddr,    vdata                    offset gds
    ds_max_u64                                 vaddr,    vdata                    offset gds
    ds_min_f32                                 vaddr,    vdata                    offset gds
    ds_min_f64                                 vaddr,    vdata                    offset gds
    ds_min_i32                                 vaddr,    vdata                    offset gds
    ds_min_i64                                 vaddr,    vdata                    offset gds
    ds_min_rtn_f32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_f64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_i32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_i64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_min_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_min_u32                                 vaddr,    vdata                    offset gds
    ds_min_u64                                 vaddr,    vdata                    offset gds
    ds_mskor_b32                               vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_b64                               vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_rtn_b32               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_mskor_rtn_b64               vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_nop
    ds_or_b32                                  vaddr,    vdata                    offset gds
    ds_or_b64                                  vaddr,    vdata                    offset gds
    ds_or_rtn_b32                  vdst,       vaddr,    vdata                    offset gds
    ds_or_rtn_b64                  vdst,       vaddr,    vdata                    offset gds
    ds_ordered_count               vdst,       vaddr                              offset gds
    ds_permute_b32                 vdst,       vaddr,    vdata                    offset
    ds_read2_b32                   vdst:b32x2, vaddr                              offset0 offset1 gds
    ds_read2_b64                   vdst:b64x2, vaddr                              offset0 offset1 gds
    ds_read2st64_b32               vdst:b32x2, vaddr                              offset0 offset1 gds
    ds_read2st64_b64               vdst:b64x2, vaddr                              offset0 offset1 gds
    ds_read_addtid_b32             vdst                                           offset gds
    ds_read_b128                   vdst,       vaddr                              offset gds
    ds_read_b32                    vdst,       vaddr                              offset gds
    ds_read_b64                    vdst,       vaddr                              offset gds
    ds_read_b96                    vdst,       vaddr                              offset gds
    ds_read_i16                    vdst,       vaddr                              offset gds
    ds_read_i8                     vdst,       vaddr                              offset gds
    ds_read_i8_d16                 vdst,       vaddr                              offset gds
    ds_read_i8_d16_hi              vdst,       vaddr                              offset gds
    ds_read_u16                    vdst,       vaddr                              offset gds
    ds_read_u16_d16                vdst,       vaddr                              offset gds
    ds_read_u16_d16_hi             vdst,       vaddr                              offset gds
    ds_read_u8                     vdst,       vaddr                              offset gds
    ds_read_u8_d16                 vdst,       vaddr                              offset gds
    ds_read_u8_d16_hi              vdst,       vaddr                              offset gds
    ds_rsub_rtn_u32                vdst,       vaddr,    vdata                    offset gds
    ds_rsub_rtn_u64                vdst,       vaddr,    vdata                    offset gds
    ds_rsub_u32                                vaddr,    vdata                    offset gds
    ds_rsub_u64                                vaddr,    vdata                    offset gds
    ds_sub_rtn_u32                 vdst,       vaddr,    vdata                    offset gds
    ds_sub_rtn_u64                 vdst,       vaddr,    vdata                    offset gds
    ds_sub_u32                                 vaddr,    vdata                    offset gds
    ds_sub_u64                                 vaddr,    vdata                    offset gds
    ds_swizzle_b32                 vdst,       vaddr                              pattern gds
    ds_wrap_rtn_b32                vdst,       vaddr,    vdata0,   vdata1         offset gds
    ds_write2_b32                              vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2_b64                              vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2st64_b32                          vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write2st64_b64                          vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_write_addtid_b32                        vdata                              offset gds
    ds_write_b128                              vaddr,    vdata                    offset gds
    ds_write_b16                               vaddr,    vdata                    offset gds
    ds_write_b16_d16_hi                        vaddr,    vdata                    offset gds
    ds_write_b32                               vaddr,    vdata                    offset gds
    ds_write_b64                               vaddr,    vdata                    offset gds
    ds_write_b8                                vaddr,    vdata                    offset gds
    ds_write_b8_d16_hi                         vaddr,    vdata                    offset gds
    ds_write_b96                               vaddr,    vdata                    offset gds
    ds_wrxchg2_rtn_b32             vdst:b32x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2_rtn_b64             vdst:b64x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2st64_rtn_b32         vdst:b32x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg2st64_rtn_b64         vdst:b64x2, vaddr,    vdata0,   vdata1         offset0 offset1 gds
    ds_wrxchg_rtn_b32              vdst,       vaddr,    vdata                    offset gds
    ds_wrxchg_rtn_b64              vdst,       vaddr,    vdata                    offset gds
    ds_xor_b32                                 vaddr,    vdata                    offset gds
    ds_xor_b64                                 vaddr,    vdata                    offset gds
    ds_xor_rtn_b32                 vdst,       vaddr,    vdata                    offset gds
    ds_xor_rtn_b64                 vdst,       vaddr,    vdata                    offset gds

### EXP

    INSTRUCTION                    DST       SRC0      SRC1      SRC2      SRC3           MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————
    exp                            tgt,      vsrc0,    vsrc1,    vsrc2,    vsrc3          done compr vm

### FLAT

    INSTRUCTION                    DST           SRC0     SRC1         SRC2       MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————————
    flat_atomic_add                vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_add_x2             vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_and                vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_and_x2             vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_cmpswap            vdst:opt,     vaddr,   vdata:b32x2             offset11 glc slc dlc
    flat_atomic_cmpswap_x2         vdst:opt,     vaddr,   vdata:b64x2             offset11 glc slc dlc
    flat_atomic_dec                vdst:opt:u32, vaddr,   vdata:u32               offset11 glc slc dlc
    flat_atomic_dec_x2             vdst:opt:u64, vaddr,   vdata:u64               offset11 glc slc dlc
    flat_atomic_fcmpswap           vdst:opt:f32, vaddr,   vdata:f32x2             offset11 glc slc dlc
    flat_atomic_fcmpswap_x2        vdst:opt:f64, vaddr,   vdata:f64x2             offset11 glc slc dlc
    flat_atomic_fmax               vdst:opt:f32, vaddr,   vdata:f32               offset11 glc slc dlc
    flat_atomic_fmax_x2            vdst:opt:f64, vaddr,   vdata:f64               offset11 glc slc dlc
    flat_atomic_fmin               vdst:opt:f32, vaddr,   vdata:f32               offset11 glc slc dlc
    flat_atomic_fmin_x2            vdst:opt:f64, vaddr,   vdata:f64               offset11 glc slc dlc
    flat_atomic_inc                vdst:opt:u32, vaddr,   vdata:u32               offset11 glc slc dlc
    flat_atomic_inc_x2             vdst:opt:u64, vaddr,   vdata:u64               offset11 glc slc dlc
    flat_atomic_or                 vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_or_x2              vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_smax               vdst:opt:i32, vaddr,   vdata:i32               offset11 glc slc dlc
    flat_atomic_smax_x2            vdst:opt:i64, vaddr,   vdata:i64               offset11 glc slc dlc
    flat_atomic_smin               vdst:opt:i32, vaddr,   vdata:i32               offset11 glc slc dlc
    flat_atomic_smin_x2            vdst:opt:i64, vaddr,   vdata:i64               offset11 glc slc dlc
    flat_atomic_sub                vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_sub_x2             vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_swap               vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_swap_x2            vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_umax               vdst:opt:u32, vaddr,   vdata:u32               offset11 glc slc dlc
    flat_atomic_umax_x2            vdst:opt:u64, vaddr,   vdata:u64               offset11 glc slc dlc
    flat_atomic_umin               vdst:opt:u32, vaddr,   vdata:u32               offset11 glc slc dlc
    flat_atomic_umin_x2            vdst:opt:u64, vaddr,   vdata:u64               offset11 glc slc dlc
    flat_atomic_xor                vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_atomic_xor_x2             vdst:opt,     vaddr,   vdata                   offset11 glc slc dlc
    flat_load_dword                vdst,         vaddr                            offset11 glc slc dlc
    flat_load_dwordx2              vdst,         vaddr                            offset11 glc slc dlc
    flat_load_dwordx3              vdst,         vaddr                            offset11 glc slc dlc
    flat_load_dwordx4              vdst,         vaddr                            offset11 glc slc dlc
    flat_load_sbyte                vdst,         vaddr                            offset11 glc slc dlc
    flat_load_sbyte_d16            vdst,         vaddr                            offset11 glc slc dlc
    flat_load_sbyte_d16_hi         vdst,         vaddr                            offset11 glc slc dlc
    flat_load_short_d16            vdst,         vaddr                            offset11 glc slc dlc
    flat_load_short_d16_hi         vdst,         vaddr                            offset11 glc slc dlc
    flat_load_sshort               vdst,         vaddr                            offset11 glc slc dlc
    flat_load_ubyte                vdst,         vaddr                            offset11 glc slc dlc
    flat_load_ubyte_d16            vdst,         vaddr                            offset11 glc slc dlc
    flat_load_ubyte_d16_hi         vdst,         vaddr                            offset11 glc slc dlc
    flat_load_ushort               vdst,         vaddr                            offset11 glc slc dlc
    flat_store_byte                              vaddr,   vdata                   offset11 glc slc dlc
    flat_store_byte_d16_hi                       vaddr,   vdata                   offset11 glc slc dlc
    flat_store_dword                             vaddr,   vdata                   offset11 glc slc dlc
    flat_store_dwordx2                           vaddr,   vdata                   offset11 glc slc dlc
    flat_store_dwordx3                           vaddr,   vdata                   offset11 glc slc dlc
    flat_store_dwordx4                           vaddr,   vdata                   offset11 glc slc dlc
    flat_store_short                             vaddr,   vdata                   offset11 glc slc dlc
    flat_store_short_d16_hi                      vaddr,   vdata                   offset11 glc slc dlc
    global_atomic_add              vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_add_x2           vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_and              vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_and_x2           vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_cmpswap          vdst:opt,     vaddr,   vdata:b32x2, saddr      offset12s glc slc dlc
    global_atomic_cmpswap_x2       vdst:opt,     vaddr,   vdata:b64x2, saddr      offset12s glc slc dlc
    global_atomic_csub             vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_dec              vdst:opt:u32, vaddr,   vdata:u32,   saddr      offset12s glc slc dlc
    global_atomic_dec_x2           vdst:opt:u64, vaddr,   vdata:u64,   saddr      offset12s glc slc dlc
    global_atomic_fcmpswap         vdst:opt:f32, vaddr,   vdata:f32x2, saddr      offset12s glc slc dlc
    global_atomic_fcmpswap_x2      vdst:opt:f64, vaddr,   vdata:f64x2, saddr      offset12s glc slc dlc
    global_atomic_fmax             vdst:opt:f32, vaddr,   vdata:f32,   saddr      offset12s glc slc dlc
    global_atomic_fmax_x2          vdst:opt:f64, vaddr,   vdata:f64,   saddr      offset12s glc slc dlc
    global_atomic_fmin             vdst:opt:f32, vaddr,   vdata:f32,   saddr      offset12s glc slc dlc
    global_atomic_fmin_x2          vdst:opt:f64, vaddr,   vdata:f64,   saddr      offset12s glc slc dlc
    global_atomic_inc              vdst:opt:u32, vaddr,   vdata:u32,   saddr      offset12s glc slc dlc
    global_atomic_inc_x2           vdst:opt:u64, vaddr,   vdata:u64,   saddr      offset12s glc slc dlc
    global_atomic_or               vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_or_x2            vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_smax             vdst:opt:i32, vaddr,   vdata:i32,   saddr      offset12s glc slc dlc
    global_atomic_smax_x2          vdst:opt:i64, vaddr,   vdata:i64,   saddr      offset12s glc slc dlc
    global_atomic_smin             vdst:opt:i32, vaddr,   vdata:i32,   saddr      offset12s glc slc dlc
    global_atomic_smin_x2          vdst:opt:i64, vaddr,   vdata:i64,   saddr      offset12s glc slc dlc
    global_atomic_sub              vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_sub_x2           vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_swap             vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_swap_x2          vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_umax             vdst:opt:u32, vaddr,   vdata:u32,   saddr      offset12s glc slc dlc
    global_atomic_umax_x2          vdst:opt:u64, vaddr,   vdata:u64,   saddr      offset12s glc slc dlc
    global_atomic_umin             vdst:opt:u32, vaddr,   vdata:u32,   saddr      offset12s glc slc dlc
    global_atomic_umin_x2          vdst:opt:u64, vaddr,   vdata:u64,   saddr      offset12s glc slc dlc
    global_atomic_xor              vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_atomic_xor_x2           vdst:opt,     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_load_dword              vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    global_load_dword_addtid       vdst,         saddr                            offset12s glc slc dlc
    global_load_dwordx2            vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_dwordx3            vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_dwordx4            vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_sbyte              vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    global_load_sbyte_d16          vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_sbyte_d16_hi       vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_short_d16          vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_short_d16_hi       vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_sshort             vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    global_load_ubyte              vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    global_load_ubyte_d16          vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_ubyte_d16_hi       vdst,         vaddr,   saddr                   offset12s glc slc dlc
    global_load_ushort             vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    global_store_byte                            vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_byte_d16_hi                     vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_dword                           vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_dword_addtid                    vdata,   saddr                   offset12s glc slc dlc
    global_store_dwordx2                         vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_dwordx3                         vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_dwordx4                         vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_short                           vaddr,   vdata,       saddr      offset12s glc slc dlc
    global_store_short_d16_hi                    vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_load_dword             vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    scratch_load_dwordx2           vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_dwordx3           vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_dwordx4           vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_sbyte             vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    scratch_load_sbyte_d16         vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_sbyte_d16_hi      vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_short_d16         vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_short_d16_hi      vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_sshort            vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    scratch_load_ubyte             vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    scratch_load_ubyte_d16         vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_ubyte_d16_hi      vdst,         vaddr,   saddr                   offset12s glc slc dlc
    scratch_load_ushort            vdst:opt,     vaddr,   saddr                   offset12s glc slc dlc lds
    scratch_store_byte                           vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_byte_d16_hi                    vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_dword                          vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_dwordx2                        vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_dwordx3                        vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_dwordx4                        vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_short                          vaddr,   vdata,       saddr      offset12s glc slc dlc
    scratch_store_short_d16_hi                   vaddr,   vdata,       saddr      offset12s glc slc dlc

### MIMG

    INSTRUCTION                 DST   SRC0       SRC1   SRC2   MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————
    image_atomic_add                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_and                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_cmpswap              vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_dec                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_fcmpswap             vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_fmax                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_fmin                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_inc                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_or                   vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_smax                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_smin                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_sub                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_swap                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_umax                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_umin                 vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_atomic_xor                  vdata:dst, vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_bvh64_intersect_ray   vdst, vaddr,     srsrc         a16
    image_bvh_intersect_ray     vdst, vaddr,     srsrc         a16
    image_gather4               vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_b             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc lwe d16
    image_gather4_b_cl          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc lwe d16
    image_gather4_b_cl_o        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc lwe d16
    image_gather4_b_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc lwe d16
    image_gather4_c             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_b           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_b_cl        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_b_cl_o      vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_b_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_cl          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_cl_o        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_l           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_l_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_lz          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_lz_o        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_c_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_cl            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_cl_o          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_l             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_l_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_lz            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_lz_o          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4_o             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 lwe d16
    image_gather4h              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe
    image_get_lod               vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe
    image_get_resinfo           vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe
    image_load                  vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_load_mip              vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_load_mip_pck          vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe
    image_load_mip_pck_sgn      vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe
    image_load_pck              vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe
    image_load_pck_sgn          vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe
    image_msaa_load             vdst, vaddr,     srsrc         dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample                vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_b              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc tfe lwe d16
    image_sample_b_cl           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc tfe lwe d16
    image_sample_b_cl_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc tfe lwe d16
    image_sample_b_o            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc tfe lwe d16
    image_sample_c              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_b            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_b_cl         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_b_cl_o       vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_b_o          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_cl        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_cl_g16    vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_cl_o      vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_cl_o_g16  vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_g16       vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cd_o_g16     vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cl           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_cl_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_cl         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_cl_g16     vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_cl_o       vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_cl_o_g16   vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_g16        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_o          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_d_o_g16      vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_l            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_l_o          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_lz           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_lz_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_c_o            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_cl          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_cl_g16      vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_cl_o        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_cl_o_g16    vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_g16         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cd_o_g16       vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cl             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_cl_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_cl           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_cl_g16       vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_cl_o         vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_cl_o_g16     vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_g16          vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_o            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_d_o_g16        vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_l              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_l_o            vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_lz             vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_lz_o           vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_sample_o              vdst, vaddr,     srsrc, ssamp  dmask dim unorm glc slc dlc a16 tfe lwe d16
    image_store                       vdata,     vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe d16
    image_store_mip                   vdata,     vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe d16
    image_store_mip_pck               vdata,     vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe
    image_store_pck                   vdata,     vaddr, srsrc  dmask dim unorm glc slc dlc a16 lwe

### MTBUF

    INSTRUCTION                    DST   SRC0   SRC1   SRC2    SRC3     MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————————————
    tbuffer_load_format_d16_x      vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_d16_xy     vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_d16_xyz    vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_d16_xyzw   vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_x          vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_xy         vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_xyz        vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_load_format_xyzw       vdst, vaddr, srsrc, soffset          ufmt idxen offen offset12 glc slc dlc
    tbuffer_store_format_d16_x           vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xy          vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xyz         vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_d16_xyzw        vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_x               vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_xy              vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_xyz             vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc
    tbuffer_store_format_xyzw            vdata, vaddr, srsrc,  soffset  ufmt idxen offen offset12 glc slc

### MUBUF

    INSTRUCTION                   DST       SRC0             SRC1   SRC2    SRC3     MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    buffer_atomic_add                       vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_add_x2                    vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_and                       vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_and_x2                    vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_cmpswap                   vdata:dst:b32x2, vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_cmpswap_x2                vdata:dst:b64x2, vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_csub                      vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_dec                       vdata:dst:u32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_dec_x2                    vdata:dst:u64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fcmpswap                  vdata:dst:f32x2, vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fcmpswap_x2               vdata:dst:f64x2, vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fmax                      vdata:dst:f32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fmax_x2                   vdata:dst:f64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fmin                      vdata:dst:f32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_fmin_x2                   vdata:dst:f64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_inc                       vdata:dst:u32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_inc_x2                    vdata:dst:u64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_or                        vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_or_x2                     vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smax                      vdata:dst:i32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smax_x2                   vdata:dst:i64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smin                      vdata:dst:i32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_smin_x2                   vdata:dst:i64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_sub                       vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_sub_x2                    vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_swap                      vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_swap_x2                   vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umax                      vdata:dst:u32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umax_x2                   vdata:dst:u64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umin                      vdata:dst:u32,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_umin_x2                   vdata:dst:u64,   vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_xor                       vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_atomic_xor_x2                    vdata:dst,       vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_gl0_inv
    buffer_gl1_inv
    buffer_load_dword             vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_load_dwordx2           vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_dwordx3           vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_dwordx4           vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_d16_x      vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_d16_xy     vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_d16_xyz    vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_d16_xyzw   vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_x          vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_load_format_xy         vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_xyz        vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_format_xyzw       vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_sbyte             vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_load_sbyte_d16         vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_sbyte_d16_hi      vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_short_d16         vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_short_d16_hi      vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_sshort            vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_load_ubyte             vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_load_ubyte_d16         vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_ubyte_d16_hi      vdst,     vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc tfe
    buffer_load_ushort            vdst:opt, vaddr,           srsrc, soffset          idxen offen offset12 glc slc dlc lds tfe
    buffer_store_byte                       vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_byte_d16_hi                vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dword                      vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx2                    vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx3                    vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_dwordx4                    vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_x               vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xy              vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xyz             vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_d16_xyzw            vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_x                   vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xy                  vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xyz                 vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_format_xyzw                vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_short                      vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc
    buffer_store_short_d16_hi               vdata,           vaddr, srsrc,  soffset  idxen offen offset12 glc slc

### SDWA

    INSTRUCTION               DST0       DST1 SRC0        SRC1       SRC2  MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add_co_ci_u32_sdwa      vdst,      vcc, src0:m,     src1:m,    vcc   clamp dst_sel dst_unused src0_sel src1_sel
    v_add_f16_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_add_f32_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_add_nc_u32_sdwa         vdst,           src0:m,     src1:m           clamp dst_sel dst_unused src0_sel src1_sel
    v_and_b32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_ashrrev_i32_sdwa        vdst,           src0:m:u32, src1:m           dst_sel dst_unused src0_sel src1_sel
    v_bfrev_b32_sdwa          vdst,           src:m                        dst_sel dst_unused src0_sel
    v_ceil_f16_sdwa           vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_ceil_f32_sdwa           vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cmp_class_f16_sdwa      sdst,           src0:m,     src1:m:b32       src0_sel src1_sel
    v_cmp_class_f32_sdwa      sdst,           src0:m,     src1:m:b32       src0_sel src1_sel
    v_cmp_eq_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_eq_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_eq_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_eq_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_eq_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_eq_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_f_f16_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_f_f32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_f_i32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_f_u32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ge_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_gt_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_le_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lg_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lg_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_f16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_f32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_lt_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ne_i16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ne_i32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ne_u16_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ne_u32_sdwa         sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_neq_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_neq_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nge_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nge_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ngt_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_ngt_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nle_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nle_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nlg_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nlg_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nlt_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_nlt_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_o_f16_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_o_f32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_t_i32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_t_u32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_tru_f16_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_tru_f32_sdwa        sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_u_f16_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmp_u_f32_sdwa          sdst,           src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_class_f16_sdwa                     src0:m,     src1:m:b32       src0_sel src1_sel
    v_cmpx_class_f32_sdwa                     src0:m,     src1:m:b32       src0_sel src1_sel
    v_cmpx_eq_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_eq_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_eq_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_eq_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_eq_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_eq_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_f_f16_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_f_f32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_f_i32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_f_u32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ge_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_gt_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_le_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lg_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lg_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_f16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_f32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_lt_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ne_i16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ne_i32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ne_u16_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ne_u32_sdwa                        src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_neq_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_neq_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nge_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nge_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ngt_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_ngt_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nle_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nle_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nlg_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nlg_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nlt_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_nlt_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_o_f16_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_o_f32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_t_i32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_t_u32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_tru_f16_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_tru_f32_sdwa                       src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_u_f16_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cmpx_u_f32_sdwa                         src0:m,     src1:m           src0_sel src1_sel
    v_cndmask_b32_sdwa        vdst,           src0:m,     src1:m,    vcc   clamp dst_sel dst_unused src0_sel src1_sel
    v_cos_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cos_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_f32_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_i16_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f16_u16_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_f16_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_i32_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_u32_sdwa        vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte0_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte1_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte2_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_f32_ubyte3_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_cvt_flr_i32_f32_sdwa    vdst,           src:m                        dst_sel dst_unused src0_sel
    v_cvt_i16_f16_sdwa        vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_cvt_i32_f32_sdwa        vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_cvt_norm_i16_f16_sdwa   vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_cvt_norm_u16_f16_sdwa   vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_cvt_off_f32_i4_sdwa     vdst,           src                          clamp omod dst_sel dst_unused src0_sel
    v_cvt_pkrtz_f16_f32_sdwa  vdst,           src0:m:f32, src1:m:f32       clamp dst_sel dst_unused src0_sel src1_sel
    v_cvt_rpi_i32_f32_sdwa    vdst,           src:m                        dst_sel dst_unused src0_sel
    v_cvt_u16_f16_sdwa        vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_cvt_u32_f32_sdwa        vdst,           src:m                        clamp dst_sel dst_unused src0_sel
    v_exp_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_exp_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_ffbh_i32_sdwa           vdst,           src:m                        dst_sel dst_unused src0_sel
    v_ffbh_u32_sdwa           vdst,           src:m                        dst_sel dst_unused src0_sel
    v_ffbl_b32_sdwa           vdst,           src:m                        dst_sel dst_unused src0_sel
    v_floor_f16_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_floor_f32_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_fract_f16_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_fract_f32_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_frexp_exp_i16_f16_sdwa  vdst,           src:m                        dst_sel dst_unused src0_sel
    v_frexp_exp_i32_f32_sdwa  vdst,           src:m                        dst_sel dst_unused src0_sel
    v_frexp_mant_f16_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_frexp_mant_f32_sdwa     vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_ldexp_f16_sdwa          vdst,           src0:m,     src1:m:i16       clamp omod dst_sel dst_unused src0_sel src1_sel
    v_log_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_log_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_lshlrev_b32_sdwa        vdst,           src0:m:u32, src1:m           dst_sel dst_unused src0_sel src1_sel
    v_lshrrev_b32_sdwa        vdst,           src0:m:u32, src1:m           dst_sel dst_unused src0_sel src1_sel
    v_max_f16_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_max_f32_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_max_i32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_max_u32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_min_f16_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_min_f32_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_min_i32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_min_u32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_mov_b32_sdwa            vdst,           src                          clamp dst_sel dst_unused src0_sel
    v_movreld_b32_sdwa        vdst,           src                          clamp dst_sel dst_unused src0_sel
    v_movrels_b32_sdwa        vdst,           vsrc                         clamp dst_sel dst_unused src0_sel
    v_movrelsd_2_b32_sdwa     vdst,           vsrc                         clamp dst_sel dst_unused src0_sel
    v_movrelsd_b32_sdwa       vdst,           vsrc                         clamp dst_sel dst_unused src0_sel
    v_mul_f16_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_mul_f32_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_mul_hi_i32_i24_sdwa     vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_mul_hi_u32_u24_sdwa     vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_mul_i32_i24_sdwa        vdst,           src0:m,     src1:m           clamp dst_sel dst_unused src0_sel src1_sel
    v_mul_legacy_f32_sdwa     vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_mul_u32_u24_sdwa        vdst,           src0:m,     src1:m           clamp dst_sel dst_unused src0_sel src1_sel
    v_not_b32_sdwa            vdst,           src:m                        dst_sel dst_unused src0_sel
    v_or_b32_sdwa             vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_rcp_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rcp_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rcp_iflag_f32_sdwa      vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rndne_f16_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rndne_f32_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rsq_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_rsq_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_sat_pk_u8_i16_sdwa      vdst:u8x4,      src:m                        dst_sel dst_unused src0_sel
    v_sin_f16_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_sin_f32_sdwa            vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_sqrt_f16_sdwa           vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_sqrt_f32_sdwa           vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_sub_co_ci_u32_sdwa      vdst,      vcc, src0:m,     src1:m,    vcc   clamp dst_sel dst_unused src0_sel src1_sel
    v_sub_f16_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_sub_f32_sdwa            vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_sub_nc_u32_sdwa         vdst,           src0:m,     src1:m           clamp dst_sel dst_unused src0_sel src1_sel
    v_subrev_co_ci_u32_sdwa   vdst,      vcc, src0:m,     src1:m,    vcc   clamp dst_sel dst_unused src0_sel src1_sel
    v_subrev_f16_sdwa         vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_subrev_f32_sdwa         vdst,           src0:m,     src1:m           clamp omod dst_sel dst_unused src0_sel src1_sel
    v_subrev_nc_u32_sdwa      vdst,           src0:m,     src1:m           clamp dst_sel dst_unused src0_sel src1_sel
    v_trunc_f16_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_trunc_f32_sdwa          vdst,           src:m                        clamp omod dst_sel dst_unused src0_sel
    v_xnor_b32_sdwa           vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel
    v_xor_b32_sdwa            vdst,           src0:m,     src1:m           dst_sel dst_unused src0_sel src1_sel

### SMEM

    INSTRUCTION                    DST       SRC0      SRC1           MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————
    s_buffer_load_dword            sdst,     sbase,    soffset        offset20u glc dlc
    s_buffer_load_dwordx16         sdst,     sbase,    soffset        offset20u glc dlc
    s_buffer_load_dwordx2          sdst,     sbase,    soffset        offset20u glc dlc
    s_buffer_load_dwordx4          sdst,     sbase,    soffset        offset20u glc dlc
    s_buffer_load_dwordx8          sdst,     sbase,    soffset        offset20u glc dlc
    s_dcache_inv
    s_gl1_inv
    s_load_dword                   sdst,     sbase,    soffset        offset21s glc dlc
    s_load_dwordx16                sdst,     sbase,    soffset        offset21s glc dlc
    s_load_dwordx2                 sdst,     sbase,    soffset        offset21s glc dlc
    s_load_dwordx4                 sdst,     sbase,    soffset        offset21s glc dlc
    s_load_dwordx8                 sdst,     sbase,    soffset        offset21s glc dlc
    s_memrealtime                  sdst:b64
    s_memtime                      sdst:b64

### SOP1

    INSTRUCTION                    DST       SRC
    ———————————————————————————————————————————————————
    s_abs_i32                      sdst,     ssrc
    s_and_saveexec_b32             sdst,     ssrc
    s_and_saveexec_b64             sdst,     ssrc
    s_andn1_saveexec_b32           sdst,     ssrc
    s_andn1_saveexec_b64           sdst,     ssrc
    s_andn1_wrexec_b32             sdst,     ssrc
    s_andn1_wrexec_b64             sdst,     ssrc
    s_andn2_saveexec_b32           sdst,     ssrc
    s_andn2_saveexec_b64           sdst,     ssrc
    s_andn2_wrexec_b32             sdst,     ssrc
    s_andn2_wrexec_b64             sdst,     ssrc
    s_bcnt0_i32_b32                sdst,     ssrc
    s_bcnt0_i32_b64                sdst,     ssrc
    s_bcnt1_i32_b32                sdst,     ssrc
    s_bcnt1_i32_b64                sdst,     ssrc
    s_bitreplicate_b64_b32         sdst,     ssrc
    s_bitset0_b32                  sdst,     ssrc
    s_bitset0_b64                  sdst,     ssrc:b32
    s_bitset1_b32                  sdst,     ssrc
    s_bitset1_b64                  sdst,     ssrc:b32
    s_brev_b32                     sdst,     ssrc
    s_brev_b64                     sdst,     ssrc
    s_cmov_b32                     sdst,     ssrc
    s_cmov_b64                     sdst,     ssrc
    s_ff0_i32_b32                  sdst,     ssrc
    s_ff0_i32_b64                  sdst,     ssrc
    s_ff1_i32_b32                  sdst,     ssrc
    s_ff1_i32_b64                  sdst,     ssrc
    s_flbit_i32                    sdst,     ssrc
    s_flbit_i32_b32                sdst,     ssrc
    s_flbit_i32_b64                sdst,     ssrc
    s_flbit_i32_i64                sdst,     ssrc
    s_getpc_b64                    sdst
    s_mov_b32                      sdst,     ssrc
    s_mov_b64                      sdst,     ssrc
    s_movreld_b32                  sdst,     ssrc
    s_movreld_b64                  sdst,     ssrc
    s_movrels_b32                  sdst,     ssrc
    s_movrels_b64                  sdst,     ssrc
    s_movrelsd_2_b32               sdst,     ssrc
    s_nand_saveexec_b32            sdst,     ssrc
    s_nand_saveexec_b64            sdst,     ssrc
    s_nor_saveexec_b32             sdst,     ssrc
    s_nor_saveexec_b64             sdst,     ssrc
    s_not_b32                      sdst,     ssrc
    s_not_b64                      sdst,     ssrc
    s_or_saveexec_b32              sdst,     ssrc
    s_or_saveexec_b64              sdst,     ssrc
    s_orn1_saveexec_b32            sdst,     ssrc
    s_orn1_saveexec_b64            sdst,     ssrc
    s_orn2_saveexec_b32            sdst,     ssrc
    s_orn2_saveexec_b64            sdst,     ssrc
    s_quadmask_b32                 sdst,     ssrc
    s_quadmask_b64                 sdst,     ssrc
    s_rfe_b64                                ssrc
    s_setpc_b64                              ssrc
    s_sext_i32_i16                 sdst,     ssrc
    s_sext_i32_i8                  sdst,     ssrc
    s_swappc_b64                   sdst,     ssrc
    s_wqm_b32                      sdst,     ssrc
    s_wqm_b64                      sdst,     ssrc
    s_xnor_saveexec_b32            sdst,     ssrc
    s_xnor_saveexec_b64            sdst,     ssrc
    s_xor_saveexec_b32             sdst,     ssrc
    s_xor_saveexec_b64             sdst,     ssrc

### SOP2

    INSTRUCTION                    DST       SRC0       SRC1
    ——————————————————————————————————————————————————————————————
    s_absdiff_i32                  sdst,     ssrc0,     ssrc1
    s_add_i32                      sdst,     ssrc0,     ssrc1
    s_add_u32                      sdst,     ssrc0,     ssrc1
    s_addc_u32                     sdst,     ssrc0,     ssrc1
    s_and_b32                      sdst,     ssrc0,     ssrc1
    s_and_b64                      sdst,     ssrc0,     ssrc1
    s_andn2_b32                    sdst,     ssrc0,     ssrc1
    s_andn2_b64                    sdst,     ssrc0,     ssrc1
    s_ashr_i32                     sdst,     ssrc0,     ssrc1:u32
    s_ashr_i64                     sdst,     ssrc0,     ssrc1:u32
    s_bfe_i32                      sdst,     ssrc0,     ssrc1:u32
    s_bfe_i64                      sdst,     ssrc0,     ssrc1:u32
    s_bfe_u32                      sdst,     ssrc0,     ssrc1
    s_bfe_u64                      sdst,     ssrc0,     ssrc1:u32
    s_bfm_b32                      sdst,     ssrc0,     ssrc1
    s_bfm_b64                      sdst,     ssrc0:b32, ssrc1:b32
    s_cselect_b32                  sdst,     ssrc0,     ssrc1
    s_cselect_b64                  sdst,     ssrc0,     ssrc1
    s_lshl1_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl2_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl3_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl4_add_u32                sdst,     ssrc0,     ssrc1
    s_lshl_b32                     sdst,     ssrc0,     ssrc1:u32
    s_lshl_b64                     sdst,     ssrc0,     ssrc1:u32
    s_lshr_b32                     sdst,     ssrc0,     ssrc1:u32
    s_lshr_b64                     sdst,     ssrc0,     ssrc1:u32
    s_max_i32                      sdst,     ssrc0,     ssrc1
    s_max_u32                      sdst,     ssrc0,     ssrc1
    s_min_i32                      sdst,     ssrc0,     ssrc1
    s_min_u32                      sdst,     ssrc0,     ssrc1
    s_mul_hi_i32                   sdst,     ssrc0,     ssrc1
    s_mul_hi_u32                   sdst,     ssrc0,     ssrc1
    s_mul_i32                      sdst,     ssrc0,     ssrc1
    s_nand_b32                     sdst,     ssrc0,     ssrc1
    s_nand_b64                     sdst,     ssrc0,     ssrc1
    s_nor_b32                      sdst,     ssrc0,     ssrc1
    s_nor_b64                      sdst,     ssrc0,     ssrc1
    s_or_b32                       sdst,     ssrc0,     ssrc1
    s_or_b64                       sdst,     ssrc0,     ssrc1
    s_orn2_b32                     sdst,     ssrc0,     ssrc1
    s_orn2_b64                     sdst,     ssrc0,     ssrc1
    s_pack_hh_b32_b16              sdst,     ssrc0:b32, ssrc1:b32
    s_pack_lh_b32_b16              sdst,     ssrc0,     ssrc1:b32
    s_pack_ll_b32_b16              sdst,     ssrc0,     ssrc1
    s_sub_i32                      sdst,     ssrc0,     ssrc1
    s_sub_u32                      sdst,     ssrc0,     ssrc1
    s_subb_u32                     sdst,     ssrc0,     ssrc1
    s_xnor_b32                     sdst,     ssrc0,     ssrc1
    s_xnor_b64                     sdst,     ssrc0,     ssrc1
    s_xor_b32                      sdst,     ssrc0,     ssrc1
    s_xor_b64                      sdst,     ssrc0,     ssrc1

### SOPC

    INSTRUCTION                    SRC0      SRC1
    ———————————————————————————————————————————————————
    s_bitcmp0_b32                  ssrc0,    ssrc1
    s_bitcmp0_b64                  ssrc0,    ssrc1:u32
    s_bitcmp1_b32                  ssrc0,    ssrc1
    s_bitcmp1_b64                  ssrc0,    ssrc1:u32
    s_cmp_eq_i32                   ssrc0,    ssrc1
    s_cmp_eq_u32                   ssrc0,    ssrc1
    s_cmp_eq_u64                   ssrc0,    ssrc1
    s_cmp_ge_i32                   ssrc0,    ssrc1
    s_cmp_ge_u32                   ssrc0,    ssrc1
    s_cmp_gt_i32                   ssrc0,    ssrc1
    s_cmp_gt_u32                   ssrc0,    ssrc1
    s_cmp_le_i32                   ssrc0,    ssrc1
    s_cmp_le_u32                   ssrc0,    ssrc1
    s_cmp_lg_i32                   ssrc0,    ssrc1
    s_cmp_lg_u32                   ssrc0,    ssrc1
    s_cmp_lg_u64                   ssrc0,    ssrc1
    s_cmp_lt_i32                   ssrc0,    ssrc1
    s_cmp_lt_u32                   ssrc0,    ssrc1

### SOPK

    INSTRUCTION                    DST       SRC0      SRC1
    —————————————————————————————————————————————————————————————
    s_addk_i32                     sdst,     imm16
    s_call_b64                     sdst,     label
    s_cmovk_i32                    sdst,     imm16
    s_cmpk_eq_i32                            ssrc,     imm16
    s_cmpk_eq_u32                            ssrc,     imm16
    s_cmpk_ge_i32                            ssrc,     imm16
    s_cmpk_ge_u32                            ssrc,     imm16
    s_cmpk_gt_i32                            ssrc,     imm16
    s_cmpk_gt_u32                            ssrc,     imm16
    s_cmpk_le_i32                            ssrc,     imm16
    s_cmpk_le_u32                            ssrc,     imm16
    s_cmpk_lg_i32                            ssrc,     imm16
    s_cmpk_lg_u32                            ssrc,     imm16
    s_cmpk_lt_i32                            ssrc,     imm16
    s_cmpk_lt_u32                            ssrc,     imm16
    s_getreg_b32                   sdst,     hwreg
    s_movk_i32                     sdst,     imm16
    s_mulk_i32                     sdst,     imm16
    s_setreg_b32                   hwreg,    ssrc
    s_setreg_imm32_b32             hwreg,    simm32
    s_subvector_loop_begin         sdst,     label
    s_subvector_loop_end           sdst,     label
    s_version                                imm16
    s_waitcnt_expcnt                         ssrc,     imm16
    s_waitcnt_lgkmcnt                        ssrc,     imm16
    s_waitcnt_vmcnt                          ssrc,     imm16
    s_waitcnt_vscnt                          ssrc,     imm16

### SOPP

    INSTRUCTION                    SRC
    —————————————————————————————————————————————
    s_barrier
    s_branch                       label
    s_cbranch_cdbgsys              label
    s_cbranch_cdbgsys_and_user     label
    s_cbranch_cdbgsys_or_user      label
    s_cbranch_cdbguser             label
    s_cbranch_execnz               label
    s_cbranch_execz                label
    s_cbranch_scc0                 label
    s_cbranch_scc1                 label
    s_cbranch_vccnz                label
    s_cbranch_vccz                 label
    s_clause                       imm16
    s_code_end
    s_decperflevel                 imm16
    s_denorm_mode                  imm16
    s_endpgm
    s_endpgm_ordered_ps_done
    s_endpgm_saved
    s_icache_inv
    s_incperflevel                 imm16
    s_inst_prefetch                imm16
    s_nop                          imm16
    s_round_mode                   imm16
    s_sendmsg                      msg
    s_sendmsghalt                  msg
    s_sethalt                      imm16
    s_setkill                      imm16
    s_setprio                      imm16
    s_sleep                        imm16
    s_trap                         imm16
    s_ttracedata
    s_ttracedata_imm               imm16
    s_waitcnt                      waitcnt
    s_waitcnt_depctr               waitcnt_depctr
    s_wakeup

### VINTRP

    INSTRUCTION                    DST       SRC0       SRC1
    ——————————————————————————————————————————————————————————————
    v_interp_mov_f32               vdst,     param:b32, attr:b32
    v_interp_p1_f32                vdst,     vsrc,      attr:b32
    v_interp_p2_f32                vdst,     vsrc,      attr:b32

### VOP1

    INSTRUCTION                    DST        SRC
    ————————————————————————————————————————————————————
    v_bfrev_b32                    vdst,      src
    v_ceil_f16                     vdst,      src
    v_ceil_f32                     vdst,      src
    v_ceil_f64                     vdst,      src
    v_clrexcp
    v_cos_f16                      vdst,      src
    v_cos_f32                      vdst,      src
    v_cvt_f16_f32                  vdst,      src
    v_cvt_f16_i16                  vdst,      src
    v_cvt_f16_u16                  vdst,      src
    v_cvt_f32_f16                  vdst,      src
    v_cvt_f32_f64                  vdst,      src
    v_cvt_f32_i32                  vdst,      src
    v_cvt_f32_u32                  vdst,      src
    v_cvt_f32_ubyte0               vdst,      src
    v_cvt_f32_ubyte1               vdst,      src
    v_cvt_f32_ubyte2               vdst,      src
    v_cvt_f32_ubyte3               vdst,      src
    v_cvt_f64_f32                  vdst,      src
    v_cvt_f64_i32                  vdst,      src
    v_cvt_f64_u32                  vdst,      src
    v_cvt_flr_i32_f32              vdst,      src
    v_cvt_i16_f16                  vdst,      src
    v_cvt_i32_f32                  vdst,      src
    v_cvt_i32_f64                  vdst,      src
    v_cvt_norm_i16_f16             vdst,      src
    v_cvt_norm_u16_f16             vdst,      src
    v_cvt_off_f32_i4               vdst,      src
    v_cvt_rpi_i32_f32              vdst,      src
    v_cvt_u16_f16                  vdst,      src
    v_cvt_u32_f32                  vdst,      src
    v_cvt_u32_f64                  vdst,      src
    v_exp_f16                      vdst,      src
    v_exp_f32                      vdst,      src
    v_ffbh_i32                     vdst,      src
    v_ffbh_u32                     vdst,      src
    v_ffbl_b32                     vdst,      src
    v_floor_f16                    vdst,      src
    v_floor_f32                    vdst,      src
    v_floor_f64                    vdst,      src
    v_fract_f16                    vdst,      src
    v_fract_f32                    vdst,      src
    v_fract_f64                    vdst,      src
    v_frexp_exp_i16_f16            vdst,      src
    v_frexp_exp_i32_f32            vdst,      src
    v_frexp_exp_i32_f64            vdst,      src
    v_frexp_mant_f16               vdst,      src
    v_frexp_mant_f32               vdst,      src
    v_frexp_mant_f64               vdst,      src
    v_log_f16                      vdst,      src
    v_log_f32                      vdst,      src
    v_mov_b32                      vdst,      src
    v_movreld_b32                  vdst,      src
    v_movrels_b32                  vdst,      vsrc
    v_movrelsd_2_b32               vdst,      vsrc
    v_movrelsd_b32                 vdst,      vsrc
    v_nop
    v_not_b32                      vdst,      src
    v_pipeflush
    v_rcp_f16                      vdst,      src
    v_rcp_f32                      vdst,      src
    v_rcp_f64                      vdst,      src
    v_rcp_iflag_f32                vdst,      src
    v_readfirstlane_b32            sdst,      src
    v_rndne_f16                    vdst,      src
    v_rndne_f32                    vdst,      src
    v_rndne_f64                    vdst,      src
    v_rsq_f16                      vdst,      src
    v_rsq_f32                      vdst,      src
    v_rsq_f64                      vdst,      src
    v_sat_pk_u8_i16                vdst:u8x4, src
    v_sin_f16                      vdst,      src
    v_sin_f32                      vdst,      src
    v_sqrt_f16                     vdst,      src
    v_sqrt_f32                     vdst,      src
    v_sqrt_f64                     vdst,      src
    v_swap_b32                     vdst,      vsrc
    v_swaprel_b32                  vdst,      vsrc
    v_trunc_f16                    vdst,      src
    v_trunc_f32                    vdst,      src
    v_trunc_f64                    vdst,      src

### VOP2

    INSTRUCTION                    DST0      DST1      SRC0        SRC1        SRC2
    —————————————————————————————————————————————————————————————————————————————————————
    v_add_co_ci_u32                vdst,     vcc,      src0,       vsrc1,      vcc
    v_add_f16                      vdst,               src0,       vsrc1
    v_add_f32                      vdst,               src0,       vsrc1
    v_add_nc_u32                   vdst,               src0,       vsrc1
    v_and_b32                      vdst,               src0,       vsrc1
    v_ashrrev_i32                  vdst,               src0:u32,   vsrc1
    v_cndmask_b32                  vdst,               src0,       vsrc1,      vcc
    v_cvt_pkrtz_f16_f32            vdst,               src0:f32,   vsrc1:f32
    v_dot2c_f32_f16                vdst,               src0:f16x2, vsrc1:f16x2
    v_dot4c_i32_i8                 vdst,               src0:i8x4,  vsrc1:i8x4
    v_fmaak_f16                    vdst,               src0,       vsrc1,      simm32
    v_fmaak_f32                    vdst,               src0,       vsrc1,      simm32
    v_fmac_f16                     vdst,               src0,       vsrc1
    v_fmac_f32                     vdst,               src0,       vsrc1
    v_fmac_legacy_f32              vdst,               src0,       vsrc1
    v_fmamk_f16                    vdst,               src0,       simm32,     vsrc2
    v_fmamk_f32                    vdst,               src0,       simm32,     vsrc2
    v_ldexp_f16                    vdst,               src0,       vsrc1:i16
    v_lshlrev_b32                  vdst,               src0:u32,   vsrc1
    v_lshrrev_b32                  vdst,               src0:u32,   vsrc1
    v_max_f16                      vdst,               src0,       vsrc1
    v_max_f32                      vdst,               src0,       vsrc1
    v_max_i32                      vdst,               src0,       vsrc1
    v_max_u32                      vdst,               src0,       vsrc1
    v_min_f16                      vdst,               src0,       vsrc1
    v_min_f32                      vdst,               src0,       vsrc1
    v_min_i32                      vdst,               src0,       vsrc1
    v_min_u32                      vdst,               src0,       vsrc1
    v_mul_f16                      vdst,               src0,       vsrc1
    v_mul_f32                      vdst,               src0,       vsrc1
    v_mul_hi_i32_i24               vdst,               src0,       vsrc1
    v_mul_hi_u32_u24               vdst,               src0,       vsrc1
    v_mul_i32_i24                  vdst,               src0,       vsrc1
    v_mul_legacy_f32               vdst,               src0,       vsrc1
    v_mul_u32_u24                  vdst,               src0,       vsrc1
    v_or_b32                       vdst,               src0,       vsrc1
    v_pk_fmac_f16                  vdst,               src0,       vsrc1
    v_sub_co_ci_u32                vdst,     vcc,      src0,       vsrc1,      vcc
    v_sub_f16                      vdst,               src0,       vsrc1
    v_sub_f32                      vdst,               src0,       vsrc1
    v_sub_nc_u32                   vdst,               src0,       vsrc1
    v_subrev_co_ci_u32             vdst,     vcc,      src0,       vsrc1,      vcc
    v_subrev_f16                   vdst,               src0,       vsrc1
    v_subrev_f32                   vdst,               src0,       vsrc1
    v_subrev_nc_u32                vdst,               src0,       vsrc1
    v_xnor_b32                     vdst,               src0,       vsrc1
    v_xor_b32                      vdst,               src0,       vsrc1

### VOP3

    INSTRUCTION               DST0        DST1  SRC0         SRC1        SRC2            MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add3_u32                vdst,             src0,        src1,       src2
    v_add_co_ci_u32_e64       vdst,       sdst, src0,        src1,       ssrc2           clamp
    v_add_co_u32              vdst,       sdst, src0,        src1                        clamp
    v_add_f16_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_add_f32_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_add_f64                 vdst,             src0:m,      src1:m                      clamp omod
    v_add_lshl_u32            vdst,             src0,        src1,       src2
    v_add_nc_i16              vdst,             src0,        src1                        op_sel clamp
    v_add_nc_i32              vdst,             src0,        src1                        clamp
    v_add_nc_u16              vdst,             src0,        src1                        op_sel clamp
    v_add_nc_u32_e64          vdst,             src0,        src1                        clamp
    v_alignbit_b32            vdst,             src0,        src1,       src2:b16
    v_alignbyte_b32           vdst,             src0,        src1,       src2:b16
    v_and_b32_e64             vdst,             src0,        src1
    v_and_or_b32              vdst,             src0,        src1,       src2
    v_ashrrev_i16             vdst,             src0:u16,    src1
    v_ashrrev_i32_e64         vdst,             src0:u32,    src1
    v_ashrrev_i64             vdst,             src0:u32,    src1
    v_bcnt_u32_b32            vdst,             src0,        src1
    v_bfe_i32                 vdst,             src0,        src1:u32,   src2:u32
    v_bfe_u32                 vdst,             src0,        src1,       src2
    v_bfi_b32                 vdst,             src0,        src1,       src2
    v_bfm_b32                 vdst,             src0,        src1
    v_bfrev_b32_e64           vdst,             src
    v_ceil_f16_e64            vdst,             src:m                                    clamp omod
    v_ceil_f32_e64            vdst,             src:m                                    clamp omod
    v_ceil_f64_e64            vdst,             src:m                                    clamp omod
    v_clrexcp_e64
    v_cmp_class_f16_e64       sdst,             src0:m,      src1:b32
    v_cmp_class_f32_e64       sdst,             src0:m,      src1:b32
    v_cmp_class_f64_e64       sdst,             src0:m,      src1:b32
    v_cmp_eq_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_eq_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_eq_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_eq_i16_e64          sdst,             src0,        src1
    v_cmp_eq_i32_e64          sdst,             src0,        src1
    v_cmp_eq_i64_e64          sdst,             src0,        src1
    v_cmp_eq_u16_e64          sdst,             src0,        src1
    v_cmp_eq_u32_e64          sdst,             src0,        src1
    v_cmp_eq_u64_e64          sdst,             src0,        src1
    v_cmp_f_f16_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_f_f32_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_f_f64_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_f_i32_e64           sdst,             src0,        src1
    v_cmp_f_i64_e64           sdst,             src0,        src1
    v_cmp_f_u32_e64           sdst,             src0,        src1
    v_cmp_f_u64_e64           sdst,             src0,        src1
    v_cmp_ge_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_ge_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_ge_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_ge_i16_e64          sdst,             src0,        src1
    v_cmp_ge_i32_e64          sdst,             src0,        src1
    v_cmp_ge_i64_e64          sdst,             src0,        src1
    v_cmp_ge_u16_e64          sdst,             src0,        src1
    v_cmp_ge_u32_e64          sdst,             src0,        src1
    v_cmp_ge_u64_e64          sdst,             src0,        src1
    v_cmp_gt_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_gt_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_gt_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_gt_i16_e64          sdst,             src0,        src1
    v_cmp_gt_i32_e64          sdst,             src0,        src1
    v_cmp_gt_i64_e64          sdst,             src0,        src1
    v_cmp_gt_u16_e64          sdst,             src0,        src1
    v_cmp_gt_u32_e64          sdst,             src0,        src1
    v_cmp_gt_u64_e64          sdst,             src0,        src1
    v_cmp_le_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_le_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_le_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_le_i16_e64          sdst,             src0,        src1
    v_cmp_le_i32_e64          sdst,             src0,        src1
    v_cmp_le_i64_e64          sdst,             src0,        src1
    v_cmp_le_u16_e64          sdst,             src0,        src1
    v_cmp_le_u32_e64          sdst,             src0,        src1
    v_cmp_le_u64_e64          sdst,             src0,        src1
    v_cmp_lg_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lg_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lg_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lt_f16_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lt_f32_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lt_f64_e64          sdst,             src0:m,      src1:m                      clamp
    v_cmp_lt_i16_e64          sdst,             src0,        src1
    v_cmp_lt_i32_e64          sdst,             src0,        src1
    v_cmp_lt_i64_e64          sdst,             src0,        src1
    v_cmp_lt_u16_e64          sdst,             src0,        src1
    v_cmp_lt_u32_e64          sdst,             src0,        src1
    v_cmp_lt_u64_e64          sdst,             src0,        src1
    v_cmp_ne_i16_e64          sdst,             src0,        src1
    v_cmp_ne_i32_e64          sdst,             src0,        src1
    v_cmp_ne_i64_e64          sdst,             src0,        src1
    v_cmp_ne_u16_e64          sdst,             src0,        src1
    v_cmp_ne_u32_e64          sdst,             src0,        src1
    v_cmp_ne_u64_e64          sdst,             src0,        src1
    v_cmp_neq_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_neq_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_neq_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nge_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nge_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nge_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_ngt_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_ngt_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_ngt_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nle_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nle_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nle_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlg_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlg_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlg_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlt_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlt_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_nlt_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_o_f16_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_o_f32_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_o_f64_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_t_i32_e64           sdst,             src0,        src1
    v_cmp_t_i64_e64           sdst,             src0,        src1
    v_cmp_t_u32_e64           sdst,             src0,        src1
    v_cmp_t_u64_e64           sdst,             src0,        src1
    v_cmp_tru_f16_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_tru_f32_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_tru_f64_e64         sdst,             src0:m,      src1:m                      clamp
    v_cmp_u_f16_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_u_f32_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmp_u_f64_e64           sdst,             src0:m,      src1:m                      clamp
    v_cmpx_class_f16_e64                        src0:m,      src1:b32
    v_cmpx_class_f32_e64                        src0:m,      src1:b32
    v_cmpx_class_f64_e64                        src0:m,      src1:b32
    v_cmpx_eq_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_eq_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_eq_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_eq_i16_e64                           src0,        src1
    v_cmpx_eq_i32_e64                           src0,        src1
    v_cmpx_eq_i64_e64                           src0,        src1
    v_cmpx_eq_u16_e64                           src0,        src1
    v_cmpx_eq_u32_e64                           src0,        src1
    v_cmpx_eq_u64_e64                           src0,        src1
    v_cmpx_f_f16_e64                            src0:m,      src1:m                      clamp
    v_cmpx_f_f32_e64                            src0:m,      src1:m                      clamp
    v_cmpx_f_f64_e64                            src0:m,      src1:m                      clamp
    v_cmpx_f_i32_e64                            src0,        src1
    v_cmpx_f_i64_e64                            src0,        src1
    v_cmpx_f_u32_e64                            src0,        src1
    v_cmpx_f_u64_e64                            src0,        src1
    v_cmpx_ge_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_ge_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_ge_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_ge_i16_e64                           src0,        src1
    v_cmpx_ge_i32_e64                           src0,        src1
    v_cmpx_ge_i64_e64                           src0,        src1
    v_cmpx_ge_u16_e64                           src0,        src1
    v_cmpx_ge_u32_e64                           src0,        src1
    v_cmpx_ge_u64_e64                           src0,        src1
    v_cmpx_gt_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_gt_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_gt_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_gt_i16_e64                           src0,        src1
    v_cmpx_gt_i32_e64                           src0,        src1
    v_cmpx_gt_i64_e64                           src0,        src1
    v_cmpx_gt_u16_e64                           src0,        src1
    v_cmpx_gt_u32_e64                           src0,        src1
    v_cmpx_gt_u64_e64                           src0,        src1
    v_cmpx_le_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_le_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_le_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_le_i16_e64                           src0,        src1
    v_cmpx_le_i32_e64                           src0,        src1
    v_cmpx_le_i64_e64                           src0,        src1
    v_cmpx_le_u16_e64                           src0,        src1
    v_cmpx_le_u32_e64                           src0,        src1
    v_cmpx_le_u64_e64                           src0,        src1
    v_cmpx_lg_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lg_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lg_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lt_f16_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lt_f32_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lt_f64_e64                           src0:m,      src1:m                      clamp
    v_cmpx_lt_i16_e64                           src0,        src1
    v_cmpx_lt_i32_e64                           src0,        src1
    v_cmpx_lt_i64_e64                           src0,        src1
    v_cmpx_lt_u16_e64                           src0,        src1
    v_cmpx_lt_u32_e64                           src0,        src1
    v_cmpx_lt_u64_e64                           src0,        src1
    v_cmpx_ne_i16_e64                           src0,        src1
    v_cmpx_ne_i32_e64                           src0,        src1
    v_cmpx_ne_i64_e64                           src0,        src1
    v_cmpx_ne_u16_e64                           src0,        src1
    v_cmpx_ne_u32_e64                           src0,        src1
    v_cmpx_ne_u64_e64                           src0,        src1
    v_cmpx_neq_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_neq_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_neq_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nge_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nge_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nge_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_ngt_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_ngt_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_ngt_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nle_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nle_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nle_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlg_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlg_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlg_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlt_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlt_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_nlt_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_o_f16_e64                            src0:m,      src1:m                      clamp
    v_cmpx_o_f32_e64                            src0:m,      src1:m                      clamp
    v_cmpx_o_f64_e64                            src0:m,      src1:m                      clamp
    v_cmpx_t_i32_e64                            src0,        src1
    v_cmpx_t_i64_e64                            src0,        src1
    v_cmpx_t_u32_e64                            src0,        src1
    v_cmpx_t_u64_e64                            src0,        src1
    v_cmpx_tru_f16_e64                          src0:m,      src1:m                      clamp
    v_cmpx_tru_f32_e64                          src0:m,      src1:m                      clamp
    v_cmpx_tru_f64_e64                          src0:m,      src1:m                      clamp
    v_cmpx_u_f16_e64                            src0:m,      src1:m                      clamp
    v_cmpx_u_f32_e64                            src0:m,      src1:m                      clamp
    v_cmpx_u_f64_e64                            src0:m,      src1:m                      clamp
    v_cndmask_b32_e64         vdst,             src0:m,      src1:m,     ssrc2
    v_cos_f16_e64             vdst,             src:m                                    clamp omod
    v_cos_f32_e64             vdst,             src:m                                    clamp omod
    v_cubeid_f32              vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_cubema_f32              vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_cubesc_f32              vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_cubetc_f32              vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_cvt_f16_f32_e64         vdst,             src:m                                    clamp omod
    v_cvt_f16_i16_e64         vdst,             src                                      clamp omod
    v_cvt_f16_u16_e64         vdst,             src                                      clamp omod
    v_cvt_f32_f16_e64         vdst,             src:m                                    clamp omod
    v_cvt_f32_f64_e64         vdst,             src:m                                    clamp omod
    v_cvt_f32_i32_e64         vdst,             src                                      clamp omod
    v_cvt_f32_u32_e64         vdst,             src                                      clamp omod
    v_cvt_f32_ubyte0_e64      vdst,             src                                      clamp omod
    v_cvt_f32_ubyte1_e64      vdst,             src                                      clamp omod
    v_cvt_f32_ubyte2_e64      vdst,             src                                      clamp omod
    v_cvt_f32_ubyte3_e64      vdst,             src                                      clamp omod
    v_cvt_f64_f32_e64         vdst,             src:m                                    clamp omod
    v_cvt_f64_i32_e64         vdst,             src                                      clamp omod
    v_cvt_f64_u32_e64         vdst,             src                                      clamp omod
    v_cvt_flr_i32_f32_e64     vdst,             src:m
    v_cvt_i16_f16_e64         vdst,             src:m                                    clamp
    v_cvt_i32_f32_e64         vdst,             src:m                                    clamp
    v_cvt_i32_f64_e64         vdst,             src:m                                    clamp
    v_cvt_norm_i16_f16_e64    vdst,             src:m                                    clamp
    v_cvt_norm_u16_f16_e64    vdst,             src:m                                    clamp
    v_cvt_off_f32_i4_e64      vdst,             src                                      clamp omod
    v_cvt_pk_i16_i32          vdst,             src0:i32,    src1:i32
    v_cvt_pk_u16_u32          vdst,             src0:u32,    src1:u32
    v_cvt_pk_u8_f32           vdst:b32,         src0:m:f32,  src1:u32,   src2:u32
    v_cvt_pknorm_i16_f16      vdst,             src0:m:f16,  src1:m:f16                  op_sel
    v_cvt_pknorm_i16_f32      vdst,             src0:m:f32,  src1:m:f32
    v_cvt_pknorm_u16_f16      vdst,             src0:m:f16,  src1:m:f16                  op_sel
    v_cvt_pknorm_u16_f32      vdst,             src0:m:f32,  src1:m:f32
    v_cvt_pkrtz_f16_f32_e64   vdst,             src0:m:f32,  src1:m:f32                  clamp
    v_cvt_rpi_i32_f32_e64     vdst,             src:m
    v_cvt_u16_f16_e64         vdst,             src:m                                    clamp
    v_cvt_u32_f32_e64         vdst,             src:m                                    clamp
    v_cvt_u32_f64_e64         vdst,             src:m                                    clamp
    v_div_fixup_f16           vdst,             src0:m,      src1:m,     src2:m          op_sel clamp omod
    v_div_fixup_f32           vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_div_fixup_f64           vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_div_fmas_f32            vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_div_fmas_f64            vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_div_scale_f32           vdst,       vcc,  src0,        src1,       src2
    v_div_scale_f64           vdst,       vcc,  src0,        src1,       src2
    v_exp_f16_e64             vdst,             src:m                                    clamp omod
    v_exp_f32_e64             vdst,             src:m                                    clamp omod
    v_ffbh_i32_e64            vdst,             src
    v_ffbh_u32_e64            vdst,             src
    v_ffbl_b32_e64            vdst,             src
    v_floor_f16_e64           vdst,             src:m                                    clamp omod
    v_floor_f32_e64           vdst,             src:m                                    clamp omod
    v_floor_f64_e64           vdst,             src:m                                    clamp omod
    v_fma_f16                 vdst,             src0:m,      src1:m,     src2:m          op_sel clamp omod
    v_fma_f32                 vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_fma_f64                 vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_fma_legacy_f32          vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_fmac_f16_e64            vdst,             src0:m,      src1:m                      clamp omod
    v_fmac_f32_e64            vdst,             src0:m,      src1:m                      clamp omod
    v_fmac_legacy_f32_e64     vdst,             src0:m,      src1:m                      clamp omod
    v_fract_f16_e64           vdst,             src:m                                    clamp omod
    v_fract_f32_e64           vdst,             src:m                                    clamp omod
    v_fract_f64_e64           vdst,             src:m                                    clamp omod
    v_frexp_exp_i16_f16_e64   vdst,             src:m
    v_frexp_exp_i32_f32_e64   vdst,             src:m
    v_frexp_exp_i32_f64_e64   vdst,             src:m
    v_frexp_mant_f16_e64      vdst,             src:m                                    clamp omod
    v_frexp_mant_f32_e64      vdst,             src:m                                    clamp omod
    v_frexp_mant_f64_e64      vdst,             src:m                                    clamp omod
    v_interp_mov_f32_e64      vdst,             param:b32,   attr:b32                    clamp omod
    v_interp_p1_f32_e64       vdst,             vsrc:m,      attr:b32                    clamp omod
    v_interp_p1ll_f16         vdst:f32,         vsrc:m:f32,  attr:b32                    high clamp omod
    v_interp_p1lv_f16         vdst:f32,         vsrc0:m:f32, attr:b32,   vsrc2:m:f16x2   high clamp omod
    v_interp_p2_f16           vdst,             vsrc0:m:f32, attr:b32,   vsrc2:m:f32     high clamp
    v_interp_p2_f32_e64       vdst,             vsrc:m,      attr:b32                    clamp omod
    v_ldexp_f16_e64           vdst,             src0:m,      src1:i16                    clamp omod
    v_ldexp_f32               vdst,             src0:m,      src1:i32                    clamp omod
    v_ldexp_f64               vdst,             src0:m,      src1:i32                    clamp omod
    v_lerp_u8                 vdst:u32,         src0:b32,    src1:b32,   src2:b32
    v_log_f16_e64             vdst,             src:m                                    clamp omod
    v_log_f32_e64             vdst,             src:m                                    clamp omod
    v_lshl_add_u32            vdst,             src0,        src1,       src2
    v_lshl_or_b32             vdst,             src0,        src1:u32,   src2
    v_lshlrev_b16             vdst,             src0:u16,    src1
    v_lshlrev_b32_e64         vdst,             src0:u32,    src1
    v_lshlrev_b64             vdst,             src0:u32,    src1
    v_lshrrev_b16             vdst,             src0:u16,    src1
    v_lshrrev_b32_e64         vdst,             src0:u32,    src1
    v_lshrrev_b64             vdst,             src0:u32,    src1
    v_mad_i16                 vdst,             src0,        src1,       src2            op_sel clamp
    v_mad_i32_i16             vdst,             src0,        src1,       src2:i32        op_sel clamp
    v_mad_i32_i24             vdst,             src0,        src1,       src2:i32        clamp
    v_mad_i64_i32             vdst,       sdst, src0,        src1,       src2:i64        clamp
    v_mad_u16                 vdst,             src0,        src1,       src2            op_sel clamp
    v_mad_u32_u16             vdst,             src0,        src1,       src2:u32        op_sel clamp
    v_mad_u32_u24             vdst,             src0,        src1,       src2:u32        clamp
    v_mad_u64_u32             vdst,       sdst, src0,        src1,       src2:u64        clamp
    v_max3_f16                vdst,             src0:m,      src1:m,     src2:m          op_sel clamp omod
    v_max3_f32                vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_max3_i16                vdst,             src0,        src1,       src2            op_sel
    v_max3_i32                vdst,             src0,        src1,       src2
    v_max3_u16                vdst,             src0,        src1,       src2            op_sel
    v_max3_u32                vdst,             src0,        src1,       src2
    v_max_f16_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_max_f32_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_max_f64                 vdst,             src0:m,      src1:m                      clamp omod
    v_max_i16                 vdst,             src0,        src1
    v_max_i32_e64             vdst,             src0,        src1
    v_max_u16                 vdst,             src0,        src1
    v_max_u32_e64             vdst,             src0,        src1
    v_mbcnt_hi_u32_b32        vdst,             src0,        src1
    v_mbcnt_lo_u32_b32        vdst,             src0,        src1
    v_med3_f16                vdst,             src0:m,      src1:m,     src2:m          op_sel clamp omod
    v_med3_f32                vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_med3_i16                vdst,             src0,        src1,       src2            op_sel
    v_med3_i32                vdst,             src0,        src1,       src2
    v_med3_u16                vdst,             src0,        src1,       src2            op_sel
    v_med3_u32                vdst,             src0,        src1,       src2
    v_min3_f16                vdst,             src0:m,      src1:m,     src2:m          op_sel clamp omod
    v_min3_f32                vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_min3_i16                vdst,             src0,        src1,       src2            op_sel
    v_min3_i32                vdst,             src0,        src1,       src2
    v_min3_u16                vdst,             src0,        src1,       src2            op_sel
    v_min3_u32                vdst,             src0,        src1,       src2
    v_min_f16_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_min_f32_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_min_f64                 vdst,             src0:m,      src1:m                      clamp omod
    v_min_i16                 vdst,             src0,        src1
    v_min_i32_e64             vdst,             src0,        src1
    v_min_u16                 vdst,             src0,        src1
    v_min_u32_e64             vdst,             src0,        src1
    v_mov_b32_e64             vdst,             src
    v_movreld_b32_e64         vdst,             src
    v_movrels_b32_e64         vdst,             vsrc
    v_movrelsd_2_b32_e64      vdst,             vsrc
    v_movrelsd_b32_e64        vdst,             vsrc
    v_mqsad_pk_u16_u8         vdst:u16x4,       src0:u8x8,   src1:u8x4,  src2:u16x4      clamp
    v_mqsad_u32_u8            vdst:u32x4,       src0:u8x8,   src1:u8x4,  vsrc2:u32x4     clamp
    v_msad_u8                 vdst:u32,         src0:b32,    src1:b32,   src2:b32        clamp
    v_mul_f16_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_mul_f32_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_mul_f64                 vdst,             src0:m,      src1:m                      clamp omod
    v_mul_hi_i32              vdst,             src0,        src1
    v_mul_hi_i32_i24_e64      vdst,             src0,        src1
    v_mul_hi_u32              vdst,             src0,        src1
    v_mul_hi_u32_u24_e64      vdst,             src0,        src1
    v_mul_i32_i24_e64         vdst,             src0,        src1                        clamp
    v_mul_legacy_f32_e64      vdst,             src0:m,      src1:m                      clamp omod
    v_mul_lo_u16              vdst,             src0,        src1
    v_mul_lo_u32              vdst,             src0,        src1
    v_mul_u32_u24_e64         vdst,             src0,        src1                        clamp
    v_mullit_f32              vdst,             src0:m,      src1:m,     src2:m          clamp omod
    v_nop_e64
    v_not_b32_e64             vdst,             src
    v_or3_b32                 vdst,             src0,        src1,       src2
    v_or_b32_e64              vdst,             src0,        src1
    v_pack_b32_f16            vdst,             src0:m,      src1:m                      op_sel
    v_perm_b32                vdst,             src0,        src1,       src2
    v_permlane16_b32          vdst,             vdata,       ssrc1,      ssrc2           dpp_op_sel
    v_permlanex16_b32         vdst,             vdata,       ssrc1,      ssrc2           dpp_op_sel
    v_pipeflush_e64
    v_qsad_pk_u16_u8          vdst:u16x4,       src0:u8x8,   src1:u8x4,  src2:u16x4      clamp
    v_rcp_f16_e64             vdst,             src:m                                    clamp omod
    v_rcp_f32_e64             vdst,             src:m                                    clamp omod
    v_rcp_f64_e64             vdst,             src:m                                    clamp omod
    v_rcp_iflag_f32_e64       vdst,             src:m                                    clamp omod
    v_readlane_b32            sdst,             src0,        ssrc1
    v_rndne_f16_e64           vdst,             src:m                                    clamp omod
    v_rndne_f32_e64           vdst,             src:m                                    clamp omod
    v_rndne_f64_e64           vdst,             src:m                                    clamp omod
    v_rsq_f16_e64             vdst,             src:m                                    clamp omod
    v_rsq_f32_e64             vdst,             src:m                                    clamp omod
    v_rsq_f64_e64             vdst,             src:m                                    clamp omod
    v_sad_hi_u8               vdst:u32,         src0:u8x4,   src1:u8x4,  src2:u32        clamp
    v_sad_u16                 vdst:u32,         src0:u16x2,  src1:u16x2, src2:u32        clamp
    v_sad_u32                 vdst,             src0,        src1,       src2            clamp
    v_sad_u8                  vdst:u32,         src0:u8x4,   src1:u8x4,  src2:u32        clamp
    v_sat_pk_u8_i16_e64       vdst:u8x4,        src
    v_sin_f16_e64             vdst,             src:m                                    clamp omod
    v_sin_f32_e64             vdst,             src:m                                    clamp omod
    v_sqrt_f16_e64            vdst,             src:m                                    clamp omod
    v_sqrt_f32_e64            vdst,             src:m                                    clamp omod
    v_sqrt_f64_e64            vdst,             src:m                                    clamp omod
    v_sub_co_ci_u32_e64       vdst,       sdst, src0,        src1,       ssrc2           clamp
    v_sub_co_u32              vdst,       sdst, src0,        src1                        clamp
    v_sub_f16_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_sub_f32_e64             vdst,             src0:m,      src1:m                      clamp omod
    v_sub_nc_i16              vdst,             src0,        src1                        op_sel clamp
    v_sub_nc_i32              vdst,             src0,        src1                        clamp
    v_sub_nc_u16              vdst,             src0,        src1                        op_sel clamp
    v_sub_nc_u32_e64          vdst,             src0,        src1                        clamp
    v_subrev_co_ci_u32_e64    vdst,       sdst, src0,        src1,       ssrc2           clamp
    v_subrev_co_u32           vdst,       sdst, src0,        src1                        clamp
    v_subrev_f16_e64          vdst,             src0:m,      src1:m                      clamp omod
    v_subrev_f32_e64          vdst,             src0:m,      src1:m                      clamp omod
    v_subrev_nc_u32_e64       vdst,             src0,        src1                        clamp
    v_trig_preop_f64          vdst,             src0:m,      src1:u32                    clamp omod
    v_trunc_f16_e64           vdst,             src:m                                    clamp omod
    v_trunc_f32_e64           vdst,             src:m                                    clamp omod
    v_trunc_f64_e64           vdst,             src:m                                    clamp omod
    v_writelane_b32           vdst,             ssrc0,       ssrc1
    v_xad_u32                 vdst,             src0,        src1,       src2
    v_xnor_b32_e64            vdst,             src0,        src1
    v_xor3_b32                vdst,             src0,        src1,       src2
    v_xor_b32_e64             vdst,             src0,        src1

### VOP3P

    INSTRUCTION          DST   SRC0        SRC1        SRC2           MODIFIERS
    ——————————————————————————————————————————————————————————————————————————————————————————————————————
    v_dot2_f32_f16       vdst, src0:f16x2, src1:f16x2, src2:f32       op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot2_i32_i16       vdst, src0:i16x2, src1:i16x2, src2:i32       op_sel op_sel_hi clamp
    v_dot2_u32_u16       vdst, src0:u16x2, src1:u16x2, src2:u32       op_sel op_sel_hi clamp
    v_dot4_i32_i8        vdst, src0:i8x4,  src1:i8x4,  src2:i32       clamp
    v_dot4_u32_u8        vdst, src0:u8x4,  src1:u8x4,  src2:u32       clamp
    v_dot8_i32_i4        vdst, src0:i4x8,  src1:i4x8,  src2:i32       clamp
    v_dot8_u32_u4        vdst, src0:u4x8,  src1:u4x8,  src2:u32       clamp
    v_fma_mix_f32        vdst, src0:m:fx,  src1:m:fx,  src2:m:fx      m_op_sel m_op_sel_hi clamp
    v_fma_mixhi_f16      vdst, src0:m:fx,  src1:m:fx,  src2:m:fx      m_op_sel m_op_sel_hi clamp
    v_fma_mixlo_f16      vdst, src0:m:fx,  src1:m:fx,  src2:m:fx      m_op_sel m_op_sel_hi clamp
    v_pk_add_f16         vdst, src0,       src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_add_i16         vdst, src0,       src1                       op_sel op_sel_hi clamp
    v_pk_add_u16         vdst, src0,       src1                       op_sel op_sel_hi clamp
    v_pk_ashrrev_i16     vdst, src0:u16x2, src1                       op_sel op_sel_hi
    v_pk_fma_f16         vdst, src0,       src1,       src2           op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_lshlrev_b16     vdst, src0:u16x2, src1                       op_sel op_sel_hi
    v_pk_lshrrev_b16     vdst, src0:u16x2, src1                       op_sel op_sel_hi
    v_pk_mad_i16         vdst, src0,       src1,       src2           op_sel op_sel_hi clamp
    v_pk_mad_u16         vdst, src0,       src1,       src2           op_sel op_sel_hi clamp
    v_pk_max_f16         vdst, src0,       src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_max_i16         vdst, src0,       src1                       op_sel op_sel_hi
    v_pk_max_u16         vdst, src0,       src1                       op_sel op_sel_hi
    v_pk_min_f16         vdst, src0,       src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_min_i16         vdst, src0,       src1                       op_sel op_sel_hi
    v_pk_min_u16         vdst, src0,       src1                       op_sel op_sel_hi
    v_pk_mul_f16         vdst, src0,       src1                       op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mul_lo_u16      vdst, src0,       src1                       op_sel op_sel_hi
    v_pk_sub_i16         vdst, src0,       src1                       op_sel op_sel_hi clamp
    v_pk_sub_u16         vdst, src0,       src1                       op_sel op_sel_hi clamp

### VOPC

    INSTRUCTION                    DST       SRC0      SRC1
    —————————————————————————————————————————————————————————————
    v_cmp_class_f16                vcc,      src0,     vsrc1:b32
    v_cmp_class_f32                vcc,      src0,     vsrc1:b32
    v_cmp_class_f64                vcc,      src0,     vsrc1:b32
    v_cmp_eq_f16                   vcc,      src0,     vsrc1
    v_cmp_eq_f32                   vcc,      src0,     vsrc1
    v_cmp_eq_f64                   vcc,      src0,     vsrc1
    v_cmp_eq_i16                   vcc,      src0,     vsrc1
    v_cmp_eq_i32                   vcc,      src0,     vsrc1
    v_cmp_eq_i64                   vcc,      src0,     vsrc1
    v_cmp_eq_u16                   vcc,      src0,     vsrc1
    v_cmp_eq_u32                   vcc,      src0,     vsrc1
    v_cmp_eq_u64                   vcc,      src0,     vsrc1
    v_cmp_f_f16                    vcc,      src0,     vsrc1
    v_cmp_f_f32                    vcc,      src0,     vsrc1
    v_cmp_f_f64                    vcc,      src0,     vsrc1
    v_cmp_f_i32                    vcc,      src0,     vsrc1
    v_cmp_f_i64                    vcc,      src0,     vsrc1
    v_cmp_f_u32                    vcc,      src0,     vsrc1
    v_cmp_f_u64                    vcc,      src0,     vsrc1
    v_cmp_ge_f16                   vcc,      src0,     vsrc1
    v_cmp_ge_f32                   vcc,      src0,     vsrc1
    v_cmp_ge_f64                   vcc,      src0,     vsrc1
    v_cmp_ge_i16                   vcc,      src0,     vsrc1
    v_cmp_ge_i32                   vcc,      src0,     vsrc1
    v_cmp_ge_i64                   vcc,      src0,     vsrc1
    v_cmp_ge_u16                   vcc,      src0,     vsrc1
    v_cmp_ge_u32                   vcc,      src0,     vsrc1
    v_cmp_ge_u64                   vcc,      src0,     vsrc1
    v_cmp_gt_f16                   vcc,      src0,     vsrc1
    v_cmp_gt_f32                   vcc,      src0,     vsrc1
    v_cmp_gt_f64                   vcc,      src0,     vsrc1
    v_cmp_gt_i16                   vcc,      src0,     vsrc1
    v_cmp_gt_i32                   vcc,      src0,     vsrc1
    v_cmp_gt_i64                   vcc,      src0,     vsrc1
    v_cmp_gt_u16                   vcc,      src0,     vsrc1
    v_cmp_gt_u32                   vcc,      src0,     vsrc1
    v_cmp_gt_u64                   vcc,      src0,     vsrc1
    v_cmp_le_f16                   vcc,      src0,     vsrc1
    v_cmp_le_f32                   vcc,      src0,     vsrc1
    v_cmp_le_f64                   vcc,      src0,     vsrc1
    v_cmp_le_i16                   vcc,      src0,     vsrc1
    v_cmp_le_i32                   vcc,      src0,     vsrc1
    v_cmp_le_i64                   vcc,      src0,     vsrc1
    v_cmp_le_u16                   vcc,      src0,     vsrc1
    v_cmp_le_u32                   vcc,      src0,     vsrc1
    v_cmp_le_u64                   vcc,      src0,     vsrc1
    v_cmp_lg_f16                   vcc,      src0,     vsrc1
    v_cmp_lg_f32                   vcc,      src0,     vsrc1
    v_cmp_lg_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_f16                   vcc,      src0,     vsrc1
    v_cmp_lt_f32                   vcc,      src0,     vsrc1
    v_cmp_lt_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_i16                   vcc,      src0,     vsrc1
    v_cmp_lt_i32                   vcc,      src0,     vsrc1
    v_cmp_lt_i64                   vcc,      src0,     vsrc1
    v_cmp_lt_u16                   vcc,      src0,     vsrc1
    v_cmp_lt_u32                   vcc,      src0,     vsrc1
    v_cmp_lt_u64                   vcc,      src0,     vsrc1
    v_cmp_ne_i16                   vcc,      src0,     vsrc1
    v_cmp_ne_i32                   vcc,      src0,     vsrc1
    v_cmp_ne_i64                   vcc,      src0,     vsrc1
    v_cmp_ne_u16                   vcc,      src0,     vsrc1
    v_cmp_ne_u32                   vcc,      src0,     vsrc1
    v_cmp_ne_u64                   vcc,      src0,     vsrc1
    v_cmp_neq_f16                  vcc,      src0,     vsrc1
    v_cmp_neq_f32                  vcc,      src0,     vsrc1
    v_cmp_neq_f64                  vcc,      src0,     vsrc1
    v_cmp_nge_f16                  vcc,      src0,     vsrc1
    v_cmp_nge_f32                  vcc,      src0,     vsrc1
    v_cmp_nge_f64                  vcc,      src0,     vsrc1
    v_cmp_ngt_f16                  vcc,      src0,     vsrc1
    v_cmp_ngt_f32                  vcc,      src0,     vsrc1
    v_cmp_ngt_f64                  vcc,      src0,     vsrc1
    v_cmp_nle_f16                  vcc,      src0,     vsrc1
    v_cmp_nle_f32                  vcc,      src0,     vsrc1
    v_cmp_nle_f64                  vcc,      src0,     vsrc1
    v_cmp_nlg_f16                  vcc,      src0,     vsrc1
    v_cmp_nlg_f32                  vcc,      src0,     vsrc1
    v_cmp_nlg_f64                  vcc,      src0,     vsrc1
    v_cmp_nlt_f16                  vcc,      src0,     vsrc1
    v_cmp_nlt_f32                  vcc,      src0,     vsrc1
    v_cmp_nlt_f64                  vcc,      src0,     vsrc1
    v_cmp_o_f16                    vcc,      src0,     vsrc1
    v_cmp_o_f32                    vcc,      src0,     vsrc1
    v_cmp_o_f64                    vcc,      src0,     vsrc1
    v_cmp_t_i32                    vcc,      src0,     vsrc1
    v_cmp_t_i64                    vcc,      src0,     vsrc1
    v_cmp_t_u32                    vcc,      src0,     vsrc1
    v_cmp_t_u64                    vcc,      src0,     vsrc1
    v_cmp_tru_f16                  vcc,      src0,     vsrc1
    v_cmp_tru_f32                  vcc,      src0,     vsrc1
    v_cmp_tru_f64                  vcc,      src0,     vsrc1
    v_cmp_u_f16                    vcc,      src0,     vsrc1
    v_cmp_u_f32                    vcc,      src0,     vsrc1
    v_cmp_u_f64                    vcc,      src0,     vsrc1
    v_cmpx_class_f16                         src0,     vsrc1:b32
    v_cmpx_class_f32                         src0,     vsrc1:b32
    v_cmpx_class_f64                         src0,     vsrc1:b32
    v_cmpx_eq_f16                            src0,     vsrc1
    v_cmpx_eq_f32                            src0,     vsrc1
    v_cmpx_eq_f64                            src0,     vsrc1
    v_cmpx_eq_i16                            src0,     vsrc1
    v_cmpx_eq_i32                            src0,     vsrc1
    v_cmpx_eq_i64                            src0,     vsrc1
    v_cmpx_eq_u16                            src0,     vsrc1
    v_cmpx_eq_u32                            src0,     vsrc1
    v_cmpx_eq_u64                            src0,     vsrc1
    v_cmpx_f_f16                             src0,     vsrc1
    v_cmpx_f_f32                             src0,     vsrc1
    v_cmpx_f_f64                             src0,     vsrc1
    v_cmpx_f_i32                             src0,     vsrc1
    v_cmpx_f_i64                             src0,     vsrc1
    v_cmpx_f_u32                             src0,     vsrc1
    v_cmpx_f_u64                             src0,     vsrc1
    v_cmpx_ge_f16                            src0,     vsrc1
    v_cmpx_ge_f32                            src0,     vsrc1
    v_cmpx_ge_f64                            src0,     vsrc1
    v_cmpx_ge_i16                            src0,     vsrc1
    v_cmpx_ge_i32                            src0,     vsrc1
    v_cmpx_ge_i64                            src0,     vsrc1
    v_cmpx_ge_u16                            src0,     vsrc1
    v_cmpx_ge_u32                            src0,     vsrc1
    v_cmpx_ge_u64                            src0,     vsrc1
    v_cmpx_gt_f16                            src0,     vsrc1
    v_cmpx_gt_f32                            src0,     vsrc1
    v_cmpx_gt_f64                            src0,     vsrc1
    v_cmpx_gt_i16                            src0,     vsrc1
    v_cmpx_gt_i32                            src0,     vsrc1
    v_cmpx_gt_i64                            src0,     vsrc1
    v_cmpx_gt_u16                            src0,     vsrc1
    v_cmpx_gt_u32                            src0,     vsrc1
    v_cmpx_gt_u64                            src0,     vsrc1
    v_cmpx_le_f16                            src0,     vsrc1
    v_cmpx_le_f32                            src0,     vsrc1
    v_cmpx_le_f64                            src0,     vsrc1
    v_cmpx_le_i16                            src0,     vsrc1
    v_cmpx_le_i32                            src0,     vsrc1
    v_cmpx_le_i64                            src0,     vsrc1
    v_cmpx_le_u16                            src0,     vsrc1
    v_cmpx_le_u32                            src0,     vsrc1
    v_cmpx_le_u64                            src0,     vsrc1
    v_cmpx_lg_f16                            src0,     vsrc1
    v_cmpx_lg_f32                            src0,     vsrc1
    v_cmpx_lg_f64                            src0,     vsrc1
    v_cmpx_lt_f16                            src0,     vsrc1
    v_cmpx_lt_f32                            src0,     vsrc1
    v_cmpx_lt_f64                            src0,     vsrc1
    v_cmpx_lt_i16                            src0,     vsrc1
    v_cmpx_lt_i32                            src0,     vsrc1
    v_cmpx_lt_i64                            src0,     vsrc1
    v_cmpx_lt_u16                            src0,     vsrc1
    v_cmpx_lt_u32                            src0,     vsrc1
    v_cmpx_lt_u64                            src0,     vsrc1
    v_cmpx_ne_i16                            src0,     vsrc1
    v_cmpx_ne_i32                            src0,     vsrc1
    v_cmpx_ne_i64                            src0,     vsrc1
    v_cmpx_ne_u16                            src0,     vsrc1
    v_cmpx_ne_u32                            src0,     vsrc1
    v_cmpx_ne_u64                            src0,     vsrc1
    v_cmpx_neq_f16                           src0,     vsrc1
    v_cmpx_neq_f32                           src0,     vsrc1
    v_cmpx_neq_f64                           src0,     vsrc1
    v_cmpx_nge_f16                           src0,     vsrc1
    v_cmpx_nge_f32                           src0,     vsrc1
    v_cmpx_nge_f64                           src0,     vsrc1
    v_cmpx_ngt_f16                           src0,     vsrc1
    v_cmpx_ngt_f32                           src0,     vsrc1
    v_cmpx_ngt_f64                           src0,     vsrc1
    v_cmpx_nle_f16                           src0,     vsrc1
    v_cmpx_nle_f32                           src0,     vsrc1
    v_cmpx_nle_f64                           src0,     vsrc1
    v_cmpx_nlg_f16                           src0,     vsrc1
    v_cmpx_nlg_f32                           src0,     vsrc1
    v_cmpx_nlg_f64                           src0,     vsrc1
    v_cmpx_nlt_f16                           src0,     vsrc1
    v_cmpx_nlt_f32                           src0,     vsrc1
    v_cmpx_nlt_f64                           src0,     vsrc1
    v_cmpx_o_f16                             src0,     vsrc1
    v_cmpx_o_f32                             src0,     vsrc1
    v_cmpx_o_f64                             src0,     vsrc1
    v_cmpx_t_i32                             src0,     vsrc1
    v_cmpx_t_i64                             src0,     vsrc1
    v_cmpx_t_u32                             src0,     vsrc1
    v_cmpx_t_u64                             src0,     vsrc1
    v_cmpx_tru_f16                           src0,     vsrc1
    v_cmpx_tru_f32                           src0,     vsrc1
    v_cmpx_tru_f64                           src0,     vsrc1
    v_cmpx_u_f16                             src0,     vsrc1
    v_cmpx_u_f32                             src0,     vsrc1
    v_cmpx_u_f64                             src0,     vsrc1