/**

  Copyright (C) 2018, Marvell International Ltd. and its affiliates.

  SPDX-License-Identifier: BSD-2-Clause-Patent

  Glossary - abbreviations used in Marvell SampleAtReset library implementation:
  ICU - Interrupt Consolidation Unit
  AP - Application Processor hardware block (Armada 7k8k incorporates AP806)
  CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110)

**/

#define CP_GIC_SPI_CP0_SDMMC           64
#define CP_GIC_SPI_PP2_CP0_PORT0       65, 68, 71, 74, 77, 90
#define CP_GIC_SPI_PP2_CP0_PORT1       66, 69, 72, 75, 78, 89
#define CP_GIC_SPI_PP2_CP0_PORT2       67, 70, 73, 76, 79, 88
#define CP_GIC_SPI_CP0_EIP_RNG0        80
#define CP_GIC_SPI_CP0_USB_H1          81
#define CP_GIC_SPI_CP0_USB_H0          82
#define CP_GIC_SPI_CP0_SATA_H0         83
#define CP_GIC_SPI_CP0_UART0           84
#define CP_GIC_SPI_CP0_UART1           85
#define CP_GIC_SPI_CP0_UART2           86
#define CP_GIC_SPI_CP0_UART3           87

#define CP_GIC_SPI_CP1_SDMMC           96
#define CP_GIC_SPI_PP2_CP1_PORT0       97, 100, 103, 106, 109, 122
#define CP_GIC_SPI_PP2_CP1_PORT1       98, 101, 104, 107, 110, 121
#define CP_GIC_SPI_PP2_CP1_PORT2       99, 102, 105, 108, 111, 120
#define CP_GIC_SPI_CP1_EIP_RNG0        112
#define CP_GIC_SPI_CP1_USB_H1          113
#define CP_GIC_SPI_CP1_USB_H0          114
#define CP_GIC_SPI_CP1_SATA_H0         115
#define CP_GIC_SPI_CP1_UART0           116
#define CP_GIC_SPI_CP1_UART1           117
#define CP_GIC_SPI_CP1_UART2           118
#define CP_GIC_SPI_CP1_UART3           119
